In recent years, it has been said in the semiconductor technical field that miniaturization (scaling) comes to have its limitations, and an improvement in performance not relying on miniaturization has been desired in the future. Examples of such a high-density packaging technology not relying on semiconductor miniaturization include a three-dimensional packaging technology in which a plurality of semiconductor chips are stacked on an interposer, for example. Further, a 2.5-dimensional packaging technology capable of manufacturing a semiconductor device more easily than the three-dimensional packaging technology has been drawing attention.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2010-73771
[Patent Document 2] Japanese Laid-open Patent Publication No. 2004-22610
[Patent Document 3] Japanese Laid-open Patent Publication No. 2009-27068
In the 2.5-dimensional packaging technology, a plurality of semiconductor chips are arranged in parallel on an interposer, and the respective semiconductor chips are electrically connected via wirings in the interposer. In this case, the distance between the semiconductor chips becomes longer as compared to the three-dimensional packaging. Therefore, a latency between the semiconductor chips increases to cause a problem that the device performance decreases as compared to the three-dimensional packaging.